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CXA1690Q
Head Amplifier for Digital CCD Cameras
Description The CXA1690Q is a bipolar IC developed as a head amplifier for digital CCD cameras. The CXA1690Q provides the following functions: correlated double sampling, AGC for CCD signals, GCA for chroma signals, GCA for line signals, sample and hold for A/D converters, blanking, and reference voltage output/output driver for A/D converters. Features * Permits higher sensitivity with a high-gain AGC amplifier * Blanking function for the purpose of calibrating the deviation in black levels of the CCD output signals * Permits output offset adjustment * Provides a regulator output pin for the reference voltage for A/D converters * Built-in GCA that amplifies video signals (chroma and line signals) from an external source * Built-in sample-and-hold circuits (for both camera signals and video signals) required by external A/D converters Absolute Maximum Ratings * Supply voltage * Operating temperature * Storage temperature * Allowable power dissipation Operating Conditions Supply voltage 32 pin QFP (Plastic)
Structure Bipolar silicon monolithic IC Applications Digital CCD cameras
VCC Topr Tstg PD
14 V -20 to +75 C -65 to +150 C 460 mW
VCC1, 2, 3
4.5 to 5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E93X02A8X-PS
CXA1690Q
Block Diagram and Pin Configuration
CCDLEVEL
AGCCONT
24
23
22
21
20
19
18
17
PIN 25 AGCCLP SH1 SH2 AGC VCC2 27 SH3 CDSCLP1 NC 28 CDSCLP2
REF BOTTOM REF TOP
AGCMAX
CLPDM
GND1
SHD
SHP
VCC1
16
AGCCLP
DIN 26
15 BLK 14
CLPOB
LPF CAMSH
XRS
13
PBLK
LINE 29 C/V SW
CAMCLP
12
OFFSET
GND2 30
LINCLP
LIN AMP
VISW VISH
11
DRV
LOUTCLP
VRT
RFCONT 31
10
VRB
RFDC PBRFC 32
RFGCA
CLPSW
9
VCC3
1
2
3
4
5
6
7
8
GND3
CSHI
VSHI
VSHP
DRVOUT
CAM/VIDEO
-2-
CLPDRV
PB/REC
CXA1690Q
Pin Description Pin No. Symbol Pin voltage H: Vcc L: GND VTH = 18 Vcc 50
1k 127 46A
(Vcc = 4.5V) Equivalent circuit Description Switches between CAM mode for the camera signal system and PB and LIN modes for the video signal system.
CAM VIDEO High Low 30k 1k PB REC Low High 100 2.4k 127 1k
Video system Video system PB mode PB mode Camera system Video system CAM mode LIN mode
1
CAM VIDEO
2
PB REC
H: Vcc L: GND VTH = 18 Vcc 50
VRT
3
VSHI
1.4V
This pin adjusts the slew rate when the video sample-and-hold circuit (VISH) built into the CXA1690 is sampling. Normally used open. R = 1K: approx. +6dB; R = 5K: approx. -6dB This pin adjusts the slew rate when the camera sample-andhold circuit (CAMSH) built into the CXA1690 is sampling. Normally used open. R = 1K: approx. +6dB; R = 5K: approx. -6dB
3k 50k 7k
4
CSHI
1.4V
100
5
VSHP
Sampling
127
Pulse input for VISH.
Typ. 2mA
18 VTH = Vcc 50
6 23 30
GND3 GND1 GND2
GND Camera system CAM mode black level: 1.3V Video system LIN mode black level: 1.4V Video system RF mode DC level: 2.2V
Driver GND. Camera signal GND. Video signal GND.
7
DRVOUT
Typ. 14mA
Driver output. Standard D range. Camera system signal: 870mVp-p Video system PB RFC signal: 500mVp-p Video system LIN signal: 1.4Vp-p
-3-
CXA1690Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
127
8
CLPDRV
Camera system CAM mode black level: 2V Video system LIN mode clamp level: 2V Video system PB mode DC level: 3V
400
LIN mode switch 50 127
CAM mode switch 78 157 86 PB mode switch 1k
Clamps and outputs the DRVOUT (Pin 7) output signal. The switch for each mode is closed and the clamp potentials applied to this pin by selecting CAMVIDEO (Pin 1) or PBRFC (Pin 2).
9 20 27
Vcc3 Vcc1 Vcc2
Vcc
Driver VCC. Camera signal VCC. Video signal VCC. 2V regulator output VRB - VRT load: 160 or greater.
16k
10
VRB
2.02V
13k 91A 6k
Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7F)
4k
1k 1.9k
4V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7F)
11
VRT
3.88V
25k
91A
91A
91A
-4-
CXA1690Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
This pin offset adjusts the CLPDRV black level when the CXA1690 satisfies the operating conditions for the camera signal system (when CAMVI is High and PBREC is Low). VCC: approx. 500mV 20/50 VCC: approx. -50mV Preset: approx. 70mV
CLPDRV offset voltage (mV)
1k 127
54k
12
OFFSET
20 Vcc to Vcc 50
125k 47k
39A
39A
500 20 50 VCC VCC OFFSET voltage (V)
70 0 -50
46A 62k 127
13
PBLK
18 VTH = Vcc 50
34k 24k 1k
Pulse input for BLK (active: Low). This pin functions only when CAMVI is High and PBREC is Low, and calibrates the black level of the AGC output waveform. When the pulse is low, the DRVOUT potential is forced to 2V. High-speed S/H pulse input for CAMSH (active: Low). High-speed S/H pulse input for SH1 (active: Low). High-speed S/H pulse input for SH2 and SH3 (active: Low).
14
XRS
VTH =
22 Vcc 50
127
200
21
SHP VTH = 25 Vcc 50
200
22
SHD
Sampling
1k
15
CLPOB
VTH =
18 Vcc 50
127
Clamp pulse input for AGCCLP (active: Low).
100
-5-
CXA1690Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
1k
2k
16
AGCCLP
Approx. 2.8V
127 41A 2k
Capacitor connection for AGCCLP clamping. 0.1 to 1F
2k 1k 127 15k 34.5k 15.5k
17
AGCMAX
Vcc to
20 Vcc 50
AGC amplifier MAX gain adjustment.
62
62
300
18
AGCCONT Vcc to
20 Vcc 50
127 4k 20.5 41 41 20k 20.5 20.5 20.5 38.4k
AGC amplifier gain adjustment. MIN GAIN 20 for VCC, MAX 50 GAIN for VCC for both AGCMAX and AGCCONT.
200
19
CCD LEVEL
DIN input CCD signal black level: approx. 2.6V
260
CCD level detector
-6-
CXA1690Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
1k 127
1k
63k
34k 86 86
24
CLPDM
VTH =
18 Vcc 50
78 63k
Clamp pulse input (active: Low).
1k 39
34k
86 127
14k
0.9
36k
25
PIN DIN
Black level: approx. 2.6V
2k
CCD signal input.
2k
1k
10k
29
LINE
Clamp potential: approx. 2.5V
127
LIN signal input.
3
200
100
-7-
CXA1690Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
4k 1k 35k
31
RFCONT
Vcc to
20 Vcc 50
127
RFGCA gain control.
42k 52k
50
100
127 7.3k 10k
100 10k
100
32
PBRFC
approx. 2.8V
PBRFC signal input.
46k
18k
41k
-8-
CXA1690Q
Electrical Characteristics Item Camera Current mode consumpLINE mode tion RF mode AGCCONT max. AGCCONT min. AGCMAX min. AGC Symbol IDC IDL IDR Conditions CAM/VIDEO = 4.5V, PB/RFC = 0V CAM/VIDEO = 0V, PB/RFC = 4.5V CAM/VIDEO = 4.5V, PB/RFC = 4.5V
(Ta = 25C, VCC1, 2, 3 = 4.5V) Min. -- -- -- 40 -- -- 32 Typ. 49 33 33 43 7.8 19 35 Max. 62 42 42 -- 10 dB 21 -- mA Unit
A CONmax. AGCMAX = 4.5V, AGCCONT = 4.5V A CONmin. A MAXmin. AGCMAX = 4.5V, AGCCONT = 1.8V AGCMAX = 1.8V, AGCCONT = 4.5V A CONmax.-A CONmin.
Amount of AGC G variation in gain
Dynamic range max. Dynamic range min. Offset High CAMCLP Offset Low Offset Preset VRT DC level REF VRB DC level VRT - VRB BLK Offset
AGCMAX = 4.5V, AGCCONT = 4.5V AGCmax. D Level at which the CLPOUT output signal is saturated AGCmin. D AGCMAX = 4.5V, AGCCONT = 1.8V Level at which the CLPOUT output signal is saturated OFFSET = 4.5V OFFSET = 1.8V OFFSET = 0V With 200 load With 200 load With 200 load BLKOF (BLK = 4.5V) - BLKOF (BLK = 0V) Adjust the DC level so that LIN input = 15kHz, 500mVp-p sine wave LINCLP. RFCONT = 4.5V, 15kHz, 80mVp-p sine wave RFCONT = 1.8V, 15kHz, 400mVp-p sine wave
1.9
2.05
-- V
1.9
2.05
--
CAOF high CAOF low CAOF pre VRTO VRBO VR BLKOF
440 -- 13 3.66 1.88 1.73 -5
490 -65 43 3.86 2.03 1.83 7
-- -30 73 4.06 2.18 1.93 15 mV V mV
LINGCA
Gain RF CONT max. RF CONT min.
LIN G RF CONmax. RF CONmin.
8.5
9.5
10.5 dB
14 --
17 0.5
-- 2
RFGCA
-9-
CXA1690Q
Electrical Characteristics Measurement Circuit
VCC
CCDLEVEL
AGCCONT
GND1
VCC1
24
23
22
21
20
19
18
AGCMAX
17 AGCCLP 0.1F
CLPDM
SHD
25 1F PIN 26 AGCCLP SH1 SH2 AGC VCC VCC2 NC 28 27 SH3 CDSCLP1 LPF CAMSH BLK
SHP
16 CLPOB 15 XRS 14 PBLK CDSCLP2
REF BOTTOM REF TOP
1F DIN
13
29 LINE 30 GND2 31 VISW LINCLP
LIN AMP
12 C/V SW
CAMCLP
OFFSET VRT 4.7 200
VISH
DRV
LOUTCLP
11 VRB 10 4.7 VCC3 VCC 9 CLPSW
RFCONT PBRFC
RFDC 32
RFGCA
0.047F 1 2 3 4 5 6 7
8
CAM/VIDEO
VSHI
CSHI
GND3
DRVOUT
1F 22
VCC
VCC
CLPDRV
20k 3V
PB/REC
VSHP
10p
Measurement Timing Chart
1H Equivalent to the black
DIN
Differs for each test
LIN PBRFC
Differs for each test
2s VCC CLPOB GND 2s VCC CLPDM GND VCC PBLK GND
- 10 -
Application Circuit
VCC VCC 50k 50k VCC
CLPDM
GND1
SHP
CCDLEVEL
SHD
VCC1
24
23 22 20 21 17
19 18
AGCCONT
AGCMAX
CLPDM
SHD
SHP
PIN 16 SH1 SH2 CLPOB 15 SH3 XRS 14 PBLK 13 VCC 12 CAMCLP DRV LOUTCLP 10 RFDC RFGCA CLPSW 9 VCC3 11 4.7F VRB 4.7F VCC 50k OFFSET VRT VRT C/V SW VISH PBLK REF BOTTOM REF TOP XRS CDSCLP1 CDSCLP2 AGC LPF CAMSH BLK AGCCLP 0.1F
AGCCLP
25
CCD
1F
DIN
26
1F
VCC
VCC2
27
NC 28
PB/ REC
VSHI
CSHI
CRM/ VIDEO
VSHP 10k VCC VCC 10k
DRVOUT
CXA1690Q
1F Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CLPDRV
1k
1k
VSHP
GND3
- 11 -
VISW LIN AMP 1 2 3 4 5 6 7 8
LIN
LINE
29
0.1F
GND2
A/D
30
LINCLP
50k
VCC
RFCONT
31
VRB A/D IN
PBRFC
PBRFC
32
0.047F
CXA1690Q
Description of Operation 1. Camera signal processing system Process the video signal processing pins as follows only in camera mode. <5> VSHP ... Connect to GND. <29> LINE ... Connect to GND via the capacitor (approx. 0.01F). <31> RFCONT ... Connect to GND. <32> PBRFC ... Connect to GND via the capacitor (approx. 0.01F). Operating conditions The camera signal processing system operates when CAM/VIDEO is High, and PB/REC is Low. Camera Signal Processing System Timing Chart
Signal interval Precharge level OPB interval Dummy pixel interval Signal interval
CCD output
Signal level SHP SHD SH1 output SH2 output SH3 output CLPDM (Dummy bit section 2 for the dummy pixel interval) AGC output -N times ( SH3 output - SH2 output ) [3] Basic black level 2.05V [1] [2] 2.6V 2.6V
2s Black level
XRS CLPOB (2 for the OPB interval)
2s
CAMSH output 2.05V PBLK (10 for the dummy pixel interval)
10s
BLK output CAMVISW output DRVOUT output [4] 2.05V - Vf 1.25V CLPDM 2s
CLPOUT output [5]
Approx. 2.1V when OFFSET is 0V 20 VCC 50 Approx. 2.5V for 50 VCC 50 Approx. 2.0V for
- 12 -
CXA1690Q
CDS: The CCD signal from the CCD image sensor enters PIN and DIN where it is correlated double sampled (CDS: Correlated Double Sampling) by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled-and-held and output by the SH2 output, and the signal level is sampled-and-held and output by the SH3 output. CDSCLP: The CDSCLP stabilizes the DC level of the input signal, clamps (CLPDM) the input signal during the dummy pixel interval for the purpose of eliminating the AGC input offset, and combines the DC level ([1], [2]) of SH2 and SH3. AGC: The gain can be varied with the AGCMAX and AGCCONT voltage control (20/50) VCC to VCC. The maximum gain can be varied from 19 to 43dB for AGCMAX, and from 7.9 to 43dB for AGCCONT. LPF: A primary low-pass filter has been installed for the purpose of eliminating unused bands and white noise and improving S/N. CAMSH: The CAMSH is used for camera system signal processing. It is a sample-and-hold circuit which synchronizes the data read-in timing for the external A/D. The slew rate of the input signal for the sample-and-hold circuit can be controlled by adjusting the input current to the CSHI pin. AGCCLP: The basic black level is set ([3]) by clamping it with the CLPOB clock during the OPB interval of the AGC output waveform. The capacitance for AGCCLP is connected to the AGCCLP pin. BLK: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential. ([4]) The signal is blanked when PBLK is low. C/VSW: When the CAM/VIDEO and PB/REC pin voltages are set so that the camera signal processing system operates, C/VSW leads the BLK output (camera signal) into the DRV. In addition, when these voltages are set so that the video signal processing system operates, C/VSW leads the VISH output (video signal) into the DRV. CLPSW: By selecting the CAM/VIDEO and PB/REC pin voltages, either [CAMCLP] is connected and lead into the CLPDRV pin as the clamp for the output signal of the camera signal processing system, or [LOUTCLP] as the clamp for the LIN mode output signal or [RFDC] as the DC shift for the PBREC mode output signal of the video signal processing system. DRV: DRV drives the external A/D. RF mode or LIN mode signals for either the camera or video signals are input to the DRV and output from DRVOUT by switching C/VSW. CAMCLP: The signal black level interval is clamped by the CLPDM clock to bring camera system signals within the allowable input voltage range for the external A/D, and the signals are output to CLPOUT. ([5]) In addition, the CAMCLP contains an OFFSET control pin which adjusts the CLP potential for the purpose of compensating the clamp level difference generated by the DRV. REFBOTTOM, REFTOP: REFBOTTOM and REFTOP are reference voltage source for the external A/D. They are connected to VRB and VRT, and supply 2V and 4V to the A/D. - 13 -
CXA1690Q
2. Video signal processing system Operating conditions The video signal processing system has two modes: LIN signal mode and PBREC signal mode. The video signal processing system operates in LIN signal mode when CAM/VIDEO is Low, and PB/REC is High. The video signal processing system operates in PBREC signal mode when PB/REC is High. Video Signal Processing System Timing Chart
LIN mode
LIN input 2.5V
LINGCA output 9.5dB
2.1V VISP
DRVOUT output (CLPDRV output)
1.4V (2V)
LIN signal mode LINCLP: The video signal enters the LIN pin. LINCLP sync tip clamps the input signal to allow full input. The input signal level and frequency are respectively 500mVp-p (typ.) and DC up to approx. 7MHz. LINAMP: This is a 9.5dB gain amplifier. VISW: VISW switches between the LIN signal and PBRFC signal for the video signal processing system. The signals are switched according to the input conditions of the CAM/VIDEO and PB/REC pins. VISH: The VISH is used for video signal processing system. It is a sample-and-hold circuit which synchronizes the data read-in timing for the external A/D. The slew rate of the input signal for the sample-and-hold circuit can be controlled by adjusting the input current to VSHI. LOUTCLP: LOUTCLP is a clamp circuit which operates when the LIN signal is output by the DRV. The clamp potential is 2V. - 14 -
CXA1690Q
PBREC signal mode RFGCA: This is an amplifier which controls the gain of the video chroma RF signal input to PBRFC. The RFCONT voltage can be varied from (20/50) VCC to VCC, enabling the gain to be varied from 0.5 to 17dB. The input signal level and frequency are respectively 200mVp-p (typ.) and DC up to approx. 1.5MHz. RFDC: RFDC is a DC bias circuit which operates when the PBREC signal is output by the DRV. The DC bias potential is 3V. PBREC mode
PBREC input
2.8V
REGCAOUT output 0.5 to 17dB
2.9V
VISH
DRVOUT output (CLPDRV output)
2.2V (3V)
- 15 -
CXA1690Q
Example of Representative Characteristics
AGCMAX control temperature characteristics
45
AGCCONT control temperature characteristics
45
VAGCMAX-Gain
40 40 VCC = 4.5V VAGCCONT = 4.5V Ta = 75C 35C -20C 30
VAGCMAX-Gain
VCC = 4.5V VAGCCONT = 4.5V
30
Gain [dB]
Gain [dB]
Ta = 75C 35C -20C 20
20
10
10
0 1.5 2 3 VAGCMAX [V] 4 4.5
0 1.5 2 3 VAGCCONT [V] 4 4.5
AGC dynamic range temperature characteristics
2200
RFGCA gain control temperature characteristics
20
Drange-T
VRFCONT-Gain
VCC = 4.500V Ta = 75C 35C -20C
D-range-AGC dynamic range [mV]
Gain [dB]
10dB dynamic range VAGCMAX = 4.5V VAGCCONT = 1.8V
10
2100
40dB dynamic range
VAGCMAX = 4.5V VAGCCONT = 4.5V
0 1.5 2
3 VRFCONT [V]
4
4.5
2000 -10
0
20
40
60
80
Ta - Temperature [C]
- 16 -
CXA1690Q
LINGCA gain control VLINCONT-Gain
VCC = 4.5V, Ta = 25C 30
CAMCLP offset temperature characteristics
504.0 T-Voff VCC = 4.5V Fig.5 502.0
When OFFSET = 4.5V 20
Gain [dB]
Voff-CAMCLP offset potential [V]
500.0 -10
0
20 40 Ta - Temperature [C]
60
75
55.0 Fig.6 54.0 53.0 -10 0 20
10
When OFFSET = 0V 40 60 75
0 1.6
2.0
3.0 VLINCONT [V]
4.0
4.5
Ta - Temperature [C] -52.0 Fig.7
-54.0 When OFFSET = 1.8V
-56.0 -10
0
20
40
60
75
Ta - Temperature [C]
- 17 -
CXA1690Q
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.24
M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
- 18 -
0.50
(8.0)

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